Embedded Avionics, Military

Multi-Core Interference Can Increase Avionics Execution Times Tenfold, Green Hills Software Says

By Frank Wolfe | March 14, 2020
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The cockpit of a Boeing B-1 bomber, which uses the Green Hills Software INTEGRITY-178 Real Time Operating System. Photo: U.S. Air Force

Multi-core interference can increase avionics system task execution times tenfold or more, according to Green Hills Software.

"We definitely have some strong viewpoints on multi-core interference," Richard Jaenicke, the marketing director of safety and security-critical products for Green Hills Software, told Avionics International in a March 11 telephone interview. "We've been pounding the drums for a while saying it's a big problem. It's actually taken a while for people to acknowledge that it's not just a little problem, but a big problem."

Green Hills has a stock of special libraries that generate interference so you can put an application on one core and then run these interference libraries on the other cores and see what's the worst case for how much interference is caused and the worst case execution time, according to Jaenicke.

"We've seen that it can be 10 times, not just two to three times worse, with only one interfering core that's doing a lot of interfering and 12 times worse, if you add in some more cores, Jaenicke said. "It can be a very big problem."

Green Hills' INTEGRITY-178 Time-Variant Unified Multi Processing (tuMP) Real Time Operating System (RTOS) uses Bandwidth Allocation and Monitoring (BAM) technology to enable the software architect to control access to shared resources by each processor core to reduce interference, the company said.

Last week, a Northrop Grumman executive discussed details with Avionics of a $59 million contract with the U.S. Air Force that features the development of an upgraded embedded GPS system for Northrop E-2D Hawkeye and Lockheed Martin F-22 Raptor aircraft that will run on the INTEGRITY-178 Time-Variant Unified Multi Processing (tuMP) RTOS with a quad-core ARM Cortex A53 central processing unit for the embedded GPS/INS-modernization (EGI-M) program. The latter, which began in 2018, is an effort to provide E-2Ds and F-22s an open-system architecture for the rapid integration of new capabilities.

In January, Green Hills announced the INTEGRITY-178 RTOS was selected by Collins Aerospace for the TCTS Inc. II program, a next generation military air combat system designed to be interoperable for joint and coalition training with fourth- and fifth-generation platforms.”

A number of other military and commercial aircraft use the INTEGRITY-178 RTOS for multi-function displays, flight control systems, navigation systems, surveillance systems, and weapons systems, such as the Boeing C-17 transport and B-1 and B-52 bombers, the 737, 747, 757, 767, and 787 airliners, the Airbus A320, A330, A340, A350, A380 airliners and the A400 M strategic lift and tactical air transport aircraft, the Northrop B-2 stealth bomber and UH-1Y and AH-1Z helicopters, the Lockheed Martin C-130J transport, the F-35 and F-16 fighters and Sikorsky S-92 and CH-148 helicopters.

Multi-core interference "is a hardware issue," Jaenicke said. "You can solve it in hardware, if you redesign the processor, but that's not going to happen so the next best thing is what's the software that interacts with the hardware and can control it? That's the operating system. At the operating system level, you can do a bunch of controls of the processors and the IO [input/output] to contain the interference."

"You can regulate the interference by regulating the bandwidth to the shared memory or the shared IO," he said. "It's really the shared memory and the shared IO or the shared DMA [direct memory access] that are causing the interference. If you throttle the bandwidth that each processor has to that, one resource hog can't take all of it and interfere with the other ones. There will still be some interference, but you can tightly bound how much you let through."

Jaenicke illustrated with an example of a quad-core processor running four separate applications simultaneously: a DAL-A safety critical application on one core, a DAL-B on another, and two non-critical applications on the two other cores. To ensure that the DAL-A process will not have interference, 50 percent of the bandwidth can be allocated to the core running the DAL-A application.

"Green Hills is the only company that's publicly talked about any mitigation strategy like this," Jaenicke said.

Typically, systems integration companies have measured multi-core interference in their systems and said that the interference in the worst case can cause execution times to be two to three times times longer than what they would normally be on a single core processor, Jaenicke said. Such companies have proposed reducing multi-core interference slightly by combining memory-intensive applications with non-memory intensive applications and giving memory-intensive applications "a three time longer time slot to run in," he said.

"There are a couple of problems with that," Jaenicke said. "What happens when you change a program and have to update an application? You don't know what the new one's going to do and how it's going to affect all the other applications. So you have to go back and re-test the whole system and hand tune it again. That's a big deal because you have to test the whole system, not just the portion that you changed. Maybe that new application has a lot more interference than the old one did. It's not two or three times [greater execution time]. It could be eight times or 10 times."

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  • Steve VanderLeest

    I can confirm that overheads due to multicore interference can be as high as the article suggests. My company (Rapita Systems) measures this interference in support of CAST-32A objectives for flight certification. While some applications might only use a small footprint of memory that fits in the L1 private cache of one core, many applications have a larger footprint that stresses shared resources in memory, such as a shared L3 cache or shared DDR main memory. In this case, the application Worst-Case Execution Time (WCET) can be quite sensitive to the use of those areas of memory by other cores, resulting in a surprisingly large impact on WCET. Careful configuration of the hardware along with a rigorous partitioning solution implemented in a trusted RTOS are key elements of a system solution to bound multicore interference.